NVIDIA Harnesses Vera CPU to Speed Up Design of Next-Generation CPUs and GPUs

As the architecture of modern semiconductors grows increasingly intricate, engineering teams are facing unprecedented challenges in developing the next generation of CPUs, GPUs, and complex AI systems. To address these bottlenecks, NVIDIA has announced a strategic collaboration with industry powerhouses Cadence and Synopsys. The goal is to optimize critical electronic design automation (EDA) applications specifically for the NVIDIA Vera CPU, a move that is already transforming how the company designs its own future silicon.

Accelerating the Pace of Innovation

The speed of chip production is a primary driver of technological progress across the entire industry. Semiconductor development relies heavily on simulation, verification, and implementation technologies, which consume years of engineering effort before a design ever reaches the manufacturing floor. While GPUs and AI have successfully accelerated various facets of chip design, many foundational EDA workloads remain tethered to CPU performance.

Tasks such as logic simulation, formal verification, and digital implementation require fast individual cores, high-bandwidth memory systems, and robust throughput. Consequently, the underlying CPU architecture serves as a critical determinant of how quickly teams can validate designs, explore architectural alternatives, and ultimately reach "tapeout."

"By using NVIDIA CPUs to help design future NVIDIA CPUs and GPUs, the company is creating a continuous feedback loop between silicon design, software optimization and systems engineering, with each generation helping build the next."

Highlighting Early Performance Gains

NVIDIA has begun deploying the Vera CPU across its internal EDA workflows, with initial testing yielding impressive results. By collaborating with Cadence and Synopsys, NVIDIA has focused on optimizing compute-intensive stages of the design cycle.

Early benchmarks on production-class workflows have demonstrated significant performance improvements:

• Cadence Jasper: This formal verification platform leverages smart proof technology and machine learning to detect bugs and enhance productivity early in the design phase.
• Synopsys VCS: A high-performance functional verification solution used to simulate and validate complex designs prior to fabrication.

In tests using an identical core count, both applications achieved up to 1.5x higher performance on selected workloads. Beyond these raw benchmarks, NVIDIA is working in tandem with both partners on deep application profiling, software optimization, and system-level tuning to ensure long-term productivity gains across a wider array of engineering tasks.

The Architecture Behind Vera

The Vera CPU is designed to meet the rigorous demands of modern engineering environments. It integrates 88 custom NVIDIA Olympus CPU cores paired with a high-efficiency LPDDR5X memory subsystem. Furthermore, it utilizes the second-generation NVIDIA Scalable Coherent Fabric, which provides the low latency and high memory bandwidth necessary for complex engineering applications.

These technical specifications are vital for workloads that require a delicate balance between latency-sensitive tasks and large-scale regression testing across massive compute farms. By shortening verification runtimes and increasing overall throughput, engineers can evaluate a greater number of design iterations within the same development window.

From RTL to Silicon: A Holistic Approach

The journey from an initial architectural concept to physical silicon involves describing behavior at the register-transfer level (RTL). This is followed by a series of interconnected workflows—including logic simulation, formal verification, and regression testing—that transform abstract designs into manufacturable products.

Because these stages are deeply linked, improvements in verification throughput have a cascading effect, allowing teams to identify and resolve issues earlier in the cycle. This reduces the frequency of costly, time-consuming downstream design iterations.

Looking Toward the Future

NVIDIA’s internal deployment of Vera reflects a broader corporate strategy: matching every specific workload with the compute architecture best suited for the task. While GPUs and AI continue to accelerate various algorithms, high-performance CPUs remain the backbone of simulation and verification.

The company is already looking ahead to the next phase of this roadmap, with plans to introduce the Rosa CPU, powered by the NVIDIA Rigel core. By continuously optimizing its EDA software stack and utilizing its own CPU technology to build future generations of processors, NVIDIA is establishing a self-reinforcing cycle of innovation. For those interested in the future of semiconductor development, further details will be showcased at DAC 2026.